N3ASIC: Designing nanofabrics with fine-grained CMOS integration

Panchapakeshan, P. and Narayanan, P. and Moritz, C. A.. (2011) N3ASIC: Designing nanofabrics with fine-grained CMOS integration. In: Nanoscale Architectures (NANOARCH), 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

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Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: CMOS integrated circuits application specific integrated circuits integrated circuit design integrated circuit interconnections nanofabrication nanowires technology CAD (electronics) three-dimensional integrated circuits 3D physics modeling CAD tools CMOS design rules N3ASIC fabric design associated circuits fine-grained CMOS integration layer-by-layer assembly sequence manufacturing constraints metal interconnects nanofabrics nanomanufacturing nanoprocessor design nanowire-CMOS fabric semiconductor nanowire array size 16 nm standard area distributed pins-vias
InterNano Taxonomy: Areas of Application > Electronics and Semiconductor Industries
Collections: Nanomanufacturing Research Collection > Nanomanufacturing Nanoscale Science and Engineering Centers > Center for Hierarchical Manufacturing
Depositing User: Robert Stevens
Date Deposited: 19 Apr 2012 21:13
Last Modified: 02 May 2012 17:24
URI: http://eprints.internano.org/id/eprint/1806

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