Rahman, M. and Narayanan, P. and Moritz, C. A.. (2011) N3ASIC Based Nanowire Volatile RAM. Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on. pp. 1097-1101.
Full text not available from this repository.Abstract
As CMOS technology advances into the nanoscale, the continuous push for low power, high performance, and dense volatile memory is reaching its limit. Moreover, in the nanometer regime complex design rules and manufacturing costs are escalating as it is getting increasingly difficult to control manufacturing process parameters. In this paper, we propose a novel 10 transistor based volatile Nanowire Random Access Memory (10T-NWRAM) which is highly scalable and manufacturing friendly since it is based on the very regular N<sup>3</sup>ASIC fabric. Besides, it has the potential to be significantly faster and low leakage alternative to SRAM since high performance nanowire FETs and dynamic logic is used for memory architecture.
| Item Type: | Article |
|---|---|
| Uncontrolled Keywords: | nanoscale |
| Collections: | Nanomanufacturing Research Collection > Nanomanufacturing Nanoscale Science and Engineering Centers > Center for Hierarchical Manufacturing |
| Depositing User: | Robert Stevens |
| Date Deposited: | 26 Mar 2014 |
| Last Modified: | 26 Mar 2014 19:44 |
| URI: | http://eprints.internano.org/id/eprint/2027 |
Actions (login required)
 |
View Item |
